Seven independent SWD debug channels, each with logic analysis, UART capture, and relay-switched power control. Flash them all. Test them all. In parallel.
Register for Early Access See How It ComparesFull CMSIS-DAP v2 debug interface over USB High Speed. Flash firmware, set breakpoints, read and write memory, reset the target. Compatible with pyOCD, OpenOCD, and probe-rs out of the box — no new toolchain to learn. All 7 channels appear as independent CMSIS-DAP probes to the host.
Digital signal capture on 8 channels per target. Verify SPI, I2C, and UART timing on the DUT's own buses. Capture pre- and post-flash to confirm peripheral initialisation. Timestamp precision to catch subtle timing regressions before they reach the field.
One full-duplex UART per channel — receive debug output, inject test commands, bridge to a connected peripheral. All 7 UART streams are captured simultaneously and forwarded to the host over the single USB connection.
Two independent relay outputs per target. Power-cycle the DUT, control test fixture interlocks, switch between voltage rails, or isolate a circuit section. Essential for boot tests, hang recovery, and sleep/wake validation. Scripted from Python — no additional hardware required.
SWD MultiProbe — version 1.
Place 7 boards in a fixture. One trigger: flash all 7 simultaneously, power-cycle via relay, run a functional test sequence — read registers over SWD, verify GPIO outputs, capture the UART startup message — compare against pass criteria, log per-board results. Cycle time per board is limited by your test, not the probe.
7 real targets running your test suite continuously. Every commit flashes all 7, runs tests in parallel, and returns a per-target result to your CI pipeline. A failing board is isolated — the others continue. 7× coverage in the time it previously took to test one.
While the functional test runs, each logic analyser records the DUT's buses. A board that passes at the register level but violates a timing constraint shows up in the capture — not as a field return six months later. Every board captured. Every board logged.
Some tests require a hard power-cycle to reproduce a boot condition or recover from a hang. Two relays per channel let you implement precise power sequencing, isolate sections of the circuit, or control fixture interlocks — all from the same Python script that controls the SWD debug and UART capture.
Scaling to 7 targets with existing tools versus a purpose-built multi-channel probe.
| 7× J-Link BASE | SWD MultiProbe | |
|---|---|---|
| SWD debug per target | ✓ | ✓ |
| Logic analyser per target | ✗ | ✓ |
| UART per target | 1× VCOM | 1× RX/TX |
| Relay power control per target | ✗ | 2× |
| Single USB connection to host | ✗ | ✓ |
| Python scripting API | ✗ | ✓ |
| Per-target pass/fail reporting | ✗ | ✓ |
| CI/CD integration | Via GDB | Native |
| Host USB ports required | 7 (+ hub) | 1 |
| 7-target cost | ~€2,800 | TBD |
The SWD MultiProbe is in development. Register to be notified when it's available to order — no commitment, one email when it ships.
Register for Early Access Multi-Target Testing Guide